Virtual ground semiconductor memory device

ABSTRACT

A semiconductor memory device includes: a memory cell region having main virtual ground lines ; and a reference cell region having reference virtual ground lines, and the reference cell region having substantially the same interconnection routine as said memory cell region, wherein, in said reference cell region, adjacent reference cells to a selected reference cell to be referred are off-bit cells.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor memory device,and more particularly to a virtual ground type read only memory device.

[0003] 2. Description of the Related Art

[0004] A virtual-grounded semiconductor memory device has been developedto reduce a chip area. Digit lines are commonly provided for pluralmemory cells. Sources and drains of adjacent memory cells are common toeach other to reduce the number of drain contacts and source contacts,thereby reducing the chip area.

[0005] A bias voltage is applied across word and digit lines designatedin accordance with an address signal, and a sense amplifier detects acurrent which flows through a designated memory cell for reading out aninformation stored in the designated memory cell. Further, a referencesignal is supplied to a differential circuit for allowing thedifferential circuit to judge “0” or “1” for the information detected bythe sense amplifier.

[0006] In case of a bank-selecting type virtual-grounded semiconductormemory device, configurations of signal lines, ground lines andpre-charge lines are changed upon changing the bank, whereby rising timeof the digit lines is also changed. As a result, a time difference fromthe reference signal is caused.

[0007] If a designated bit is adjacent to two ON-bit lines, capacitancesof diffusion layers of ON-bit cells are added to a current path, wherebythe necessary sense amplifier current or reference current forcharging-up the increased capacitance is temporary increased.

[0008] The technical term “ON-bit cell” means a cell transistor having alower threshold voltage than a word line voltage. The technical term“OFF-bit cell” means a cell transistor having a higher threshold voltagethan a word line voltage.

[0009]FIG. 1A is a circuit diagram of a reference cell region of aconventional virtual-grounded semiconductor memory device. The referencecell region includes two bank selecting lines BS, and transistors Trb0,Trb1, Trb2, and Trb3. Gates of the transistors Trb0, Trb1, Trb2, andTrb3 are connected to the bank selecting lines BS. Sources of thetransistors Trb0, Trb1, Trb2, and Trb3 are connected to digit lines.Drains of the transistors Trb0, Trb1, Trb2, and Trb3 arc commonlyconnected to reference digit lines RD0 and RD1.

[0010] The reference cell region further includes word lines connectedto an X-decoder which is not illustrated, and four ground selectinglines GS connected to gates of transistors Trg0, Trg1, Trg2, Trg3, andTrg4. Drains of the transistors Trg0, Trg1, Trg2, Trg3, and Trg4 areconnected to subordinate ground lines for the reference cells. Sourcesof the transistors Trg0, Trg1, Trg2 and Trg3 are commonly connected to areference virtual ground line RVG1. A source of the transistor Trg4 isconnected to a reference virtual ground line RVG2.

[0011] The bank selecting lines BS and the ground selecting lines GS areindependent from the X-decoder. In order to select a single bank BANK3,the bank selecting line and the ground selecting line are fixed at highlevel for placing the transistors Trb1 and Trg2 in ON-state.

[0012] The bank BANK3 has the ON-bit cells and the remaining banks havethe OFF-bit cells, for which reason the capacitances of the subordinatedigit lines and the subordinate virtual ground lines of the remainingbanks are not added.

[0013]FIG. 1B is a diagram of time-dependent variations in voltage ofselected digit lines and reference digit lines when a bank havingOFF-bit cells is selected in the reference cell region of FIG. 1A. Thereference digit line is charged-up faster than the selected digit line.If the OFF-bit cell of the memory cell region is selected, the readingout operation from the OFF-bit cell is delayed. The delay in reading outoperation may be caused depending on the bank. This delay may be socalled to as bank dependency.

[0014]FIG. 2A is a circuit diagram of another reference cell region ofthe conventional semiconductor memory device. The other reference cellregion of FIG. 2A is structurally different from the above referencecell region of FIG. 1A in the following points. The bank selecting linesBS and the ground selecting lines GS are also connected to the X-decoderwhich is not illustrated. Further, all of the reference cells are ON-bitcells.

[0015] Changing the bank makes the bank-dependency of the flat cells tothe memory cells. All of the cells on the same word line are thus ON-bitcells. The capacitances of the subordinate digit lines and thesubordinate virtual ground lines arc added through the adjacent ON-bitcells to the reference current path.

[0016]FIG. 2B is a diagram of time-dependent variations of referencecurrent IRA and sense amplifier current when a memory cell adjacent toOFF-bit cells is selected in the reference cell region of FIG. 2A. Ifthe sense amplifier current is transitionally insufficient, thereference current IRA is transitionally larger than the sense amplifiercurrent ISA′. The judgement to the ON-bit cell by the differentialcircuit is delayed. The reading out speed or the ON-judgement speed bythe sense amplifier is delayed depending on code patterns. This delaymay be so called to as code pattern dependency.

[0017] In the above circumstances, the development of a novelsemiconductor memory device free from the above problems is desirable.

SUMMARY OF THE INVENTION

[0018] Accordingly, it is an object of the present invention to providea novel semiconductor memory device free from the above problems.

[0019] It is a further object of the present invention to provide anovel semiconductor memory device free of bank dependency.

[0020] It is a still further object of the present invention to providea novel semiconductor memory device free of code pattern dependency.

[0021] It is yet a further object of the present invention to provide anovel semiconductor memory device exhibiting higher speed read-outoperation.

[0022] The present invention provides a semiconductor memory deviceincluding: a memory cell region including main memory cells, main digitlines, and main virtual ground lines, and the memory cell regionpossessing a first current routine pattern through the main digit lineto the main memory cell designated in accordance with a address signal;and a reference cell region including reference memory cells, referencedigit lines, and reference virtual ground lines, and the reference cellregion possessing a second current routine pattern through the referencedigit line to the reference memory cell in accordance with the addresssignal, wherein the first current routine pattern is always identicalwith the second current routine pattern upon designating any memory celladdresses.

[0023] The above and other objects, features and advantages of thepresent invention will be apparent from the following descriptions.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Preferred embodiments according to the present invention will bedescribed in detail with reference to the accompanying drawings.

[0025]FIG. 1A is a circuit diagram of a reference cell region of aconventional virtual-grounded semiconductor memory device.

[0026]FIG. 1B is a diagram of time-dependent variations in voltage ofselected digit lines and reference digit lines when a bank havingOFF-bit cells is selected in the reference cell region of FIG. 1A.

[0027]FIG. 2A is a circuit diagram of another reference cell region ofthe conventional semiconductor memory device.

[0028]FIG. 2B is a diagram of time-dependent variations of referencecurrent IRA and sense amplifier current when a memory cell adjacent toOFF-bit cells is selected in the reference cell region of FIG. 2A.

[0029]FIG. 3 is a block diagram of a semiconductor memory device in afirst embodiment in accordance with the present invention.

[0030]FIG. 4 is a fragmentary circuit diagram of the memory cell regionhaving a flat-cell structure in the semiconductor device of FIG. 3.

[0031]FIG. 5 is a fragmentary circuit diagram of the Y-selector circuitin the semiconductor memory device of FIG. 3.

[0032]FIG. 6 is a fragmentary circuit diagram of the virtual groundselector circuit in the semiconductor memory device of FIG. 3.

[0033]FIG. 7 is a table of truth values for selecting banks of thememory cell region in the semiconductor memory device of FIG. 3.

[0034]FIG. 8 is a circuit diagram of the reference cell region of thesemiconductor memory device of FIG. 3.

[0035]FIG. 9 is a circuit diagram of the dummy Y-selector circuit of thesemiconductor memory device of FIG. 3.

[0036]FIG. 10 is a circuit diagram of the dummy virtual ground selectorcircuit of the semiconductor memory device of FIG. 3.

[0037]FIG. 11 is a table of truth values for selecting banks of thereference cell region in the semiconductor memory device of FIG. 3.

[0038]FIG. 12 is a view of respective positional inter-relationshipsbetween main digit lines and main virtual ground lines for variousbanks.

[0039]FIG. 13 is a diagram of time-variations in voltage of the selecteddigit lines upon selecting the respective eight banks.

[0040]FIG. 14A is a diagram of time-dependent variations in senseamplifier currents ISA from the sense amplifiers and in reference senseamplifier currents IRA from the reference sense amplifiers when a mainmemory cell “A” is selected, wherein adjacent cells are ON-bit cells.

[0041]FIG. 14B is a diagram of time-dependent variations in senseamplifier currents ISA from the sense amplifiers and in reference senseamplifier currents IRA from the reference sense amplifiers when anothermain memory cell “A′” is selected, wherein adjacent cells are OFF-bitcells.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0042] A first aspect of the present invention is a semiconductor memorydevice including: a memory cell region having main virtual ground lines,and the memory cell region exhibiting a first current path pattern onmain digit lines, upon designating a memory cell address ; and areference cell region having reference virtual ground lines, and thereference cell region having substantially the same interconnectionroutine as the memory cell region, the reference cell region exhibitinga second current path pattern on reference digit lines, upon designatingthe memory cell address, the second current path pattern being identicalwith the first current path pattern, wherein the current path pattern ofthe reference cell region is always kept corresponding to the currentpath pattern of the memory cell region upon designating any memory celladdresses.

[0043] It is possible that the semiconductor memory device may furthercomprise a current detecting circuit, and wherein the memory cell regionincludes main virtual ground lines and main digit lines, and at leastfirst one of the main digit lines is selectively connected to thecurrent detecting circuit, and at least first one of the main virtualground lines is selectively connected to a ground line, and the at leastfirst one main digit line connected to the current detecting circuit andthe at least first one main virtual ground line connected to the groundline form a first main current route, and wherein the reference cellregion further includes reference digit lines, and at least first one ofthe reference digit lines is selectively connected to the currentdetecting circuit, and at least first one of the reference virtualground lines is selectively connected to the ground line, and the atleast first one reference digit line connected to the current detectingcircuit and the at least first one reference virtual ground lineconnected to the ground line form a first reference current route, whichis identical with the first main current route.

[0044] It is possible that the semiconductor memory device may furthercomprise : a main digit line selector circuit for selecting at least oneof the main digit lines, so that the selected at least one main digitline is connected to the current detecting circuit; and a referencedigit line selector circuit for selecting at least one of the referencedigit lines, so that the selected at least one reference digit line isalso connected to the current detecting circuit.

[0045] It is possible that the semiconductor memory device may furthercomprise: a main virtual ground line selector circuit for selecting atleast one of the main virtual ground lines, so that the selected atleast one main virtual ground line is connected to a ground line ; and areference virtual ground selector circuit for selecting at least one ofthe reference virtual ground lines, so that the selected at least onereference virtual ground line is also connected to the ground line.

[0046] It is possible that the memory cell region further includessubordinate memory digit lines, and the reference cell region furtherincludes subordinate reference digit lines, and the semiconductor memorydevice may further comprise a bank selecting circuit for selecting atleast one of the subordinate memory digit lines, so that the selected atleast one subordinate memory digit line is connected to the main digitline, and further selecting at least one of the subordinate referencedigit lines, so that the selected at least one subordinate referencedigit line is connected to the reference digit line.

[0047] It is possible that the semiconductor memory device may furthercomprise a main pre-charge circuit, and wherein at least second one ofthe main digit lines is selected and connected to the main pre-chargecircuit, and wherein the at least first one main digit line connected tothe current detecting circuit, the at least second one of the main digitline connected to the main pre-charge circuit, and the at least firstone main virtual ground line connected to the ground line form a secondmain current route, and wherein at least second one of the referencedigit lines is selected and connected to the main pre-charge circuit,and wherein the at least first one reference digit line connected to thecurrent detecting circuit, the at least second one reference digit lineconnected to the main pre-charge circuit, and the at least first onereference virtual ground line connected to the ground line form a firstreference current route, which is identical with the first main currentroute.

[0048] It is possible that the semiconductor memory device may furthercomprise a subordinate pre-charge circuit, and wherein at least secondone of the main virtual ground lines is selected and connected to thesubordinate pre-charge circuit, and wherein the at least first one maindigit line connected to the current detecting circuit, the at leastsecond one of the main digit line connected to the subordinatepre-charge circuit, the at least first one main virtual ground lineconnected to the ground line, and the second one main virtual groundline form a third main current route, and wherein at least second one ofthe reference virtual ground lines is selected and connected to thesubordinate pre-charge circuit, and wherein the at least first onereference digit line connected to the current detecting Circuit, the atleast second one reference digit line connected to the subordinatepre-charge circuit, the at least first one reference virtual ground lineconnected to the ground line, and the at least second one referencevirtual ground line form a fourth reference current route, which isidentical with the third main current route,

[0049] It is possible that the semiconductor memory device may furthercomprise : subordinate memory digit lines in the memory cell region;subordinate reference digit lines in the reference cell region; and atleast a bank selecting circuit for selecting at least one of thesubordinate memory digit lines and connecting the selected at least onesubordinate memory digit line to the main digit line, as well as forselecting at least one of the subordinate reference digit lines andconnecting the selected at least one subordinate reference digit line tothe reference digit line.

[0050] It is possible that in the reference cell region, adjacentreference cells to a selected reference cell to be referred are off-bitcells.

[0051] It is possible that the reference cell region includes adjacentfirst and second subordinate regions, and the first subordinate regionhas even number banks having ON-bit cells and odd number banks havingOFF-bit cells, and the second subordinate region has even number bankshaving OFF-bit cells and odd number banks having ON-bit cells.

[0052] A second aspect of the present invention is a semiconductormemory device including: a memory cell region including main memorycells, main digit lines, and main virtual ground lines, and the memorycell region possessing a first current routine pattern through the maindigit line to the main memory cell designated in accordance with aaddress signal and a reference cell region including reference memorycells, reference digit lines, and reference virtual ground lines, andthe reference cell region possessing a second current routine patternthrough the reference digit line to the reference memory cell inaccordance with the address signal, wherein the first current routinepattern is always identical with the second current routine pattern upondesignating any memory cell addresses.

[0053] This second aspect of the present invention has the samepreferable practicable modes described above in connection with thefirst aspect of the present invention.

[0054] A third aspect of the present invention is a semiconductor memorydevice including a memory cell region having main digit lines and mainvirtual ground lines; and a reference cell region having reference digitlines and reference virtual ground lines, and the reference cell regionhaving substantially the same interconnection routine as the memory cellregion, a current detecting circuit; a main digit line selector circuitfor selecting at least one of the main digit lines, so that the selectedat least one main digit line is connected to the current detectingcircuit; and a reference digit line selector circuit for selecting atleast one of the reference digit lines, so that the selected at leastone reference digit line is also connected to the current detectingcircuit ; a main virtual ground line selector circuit for selecting atleast one of the main virtual ground lines, so that the selected atleast one main virtual ground line is connected to a ground line; areference virtual ground selector circuit for selecting at least one ofthe reference virtual ground lines, so that the selected at least onereference virtual ground line is also connected to the ground line ;wherein the at least first one main digit line connected to the currentdetecting circuit and the at least first one main virtual ground lineconnected to the ground line form a first main current route, andwherein the at least first one reference digit line connected to thecurrent detecting circuit and the at least first one reference virtualground line connected to the ground line form a first reference currentroute, which is identical with the first main current route.

[0055] This third aspect of the present invention has the samepreferable practicable modes described above in connection with thefirst aspect of the present invention.

[0056] A fourth aspect of the present invention is a semiconductormemory device including a memory cell region having main digit lines,main virtual ground lines, and subordinate memory digit lines; and areference cell region having reference digit lines, reference virtualground lines, and subordinate reference digit lines, and the referencecell region having substantially the same interconnection routine as thememory cell region, wherein adjacent reference cells to a selectedreference cell to be referred are off-bit cells, at least a bankselecting circuit for selecting at least one of the subordinate memorydigit lines and connecting the selected at least one subordinate memorydigit line to the main digit line, as well as for selecting at least oneof the subordinate reference digit lines and connecting the selected atleast one subordinate reference digit line to the reference digit line ;a current detecting circuit ; a main digit line selector circuit forselecting at least one of the main digit lines, so that the selected atleast one main digit line is connected to the current detecting circuit;a reference digit line selector circuit for selecting at least one ofthe reference digit lines, so that the selected at least one referencedigit line is also connected to the current detecting circuit ; a mainvirtual ground line selector circuit for selecting at least one of themain virtual ground lines, so that the selected at least one mainvirtual ground line is connected to a ground line ; and a referencevirtual ground selector circuit for selecting at least one of thereference virtual ground lines, so that the selected at least onereference virtual ground line is also connected to the ground line,wherein the at least first one main digit line connected to the currentdetecting circuit and the at least first one main virtual ground lineconnected to the ground line form a first main current route, andwherein the at least first one reference digit line connected to thecurrent detecting circuit and the at least first one reference virtualground line connected to the ground line form a first reference currentroute, which is identical with the first main current route.

[0057] This fourth aspect of the present invention has the samepreferable practicable modes described above in connection with thefirst aspect of the present invention.

[0058] A fifth aspect of the present invention is a semiconductor memorydevice including: a memory cell region having main virtual ground lines; and a reference cell region having reference virtual ground lines, andthe reference cell region having substantially the same interconnectionroutine as the memory cell region, wherein the reference cell regionincludes adjacent first and second subordinate regions, and the firstsubordinate region having even number banks having ON-bit cells and oddnumber banks having OFF-bit cells, and the second subordinate regionhaving even number banks having OFF-bit cells and odd number bankshaving ON-bit cells.

[0059] This fifth aspect of the present invention has the samepreferable practicable modes described above in connection with thefirst aspect of the present invention.

[0060] A sixth aspect of the present invention is a semiconductor memorydevice comprising : a memory cell region including a plurality of mainbanks, each having memory cells, main digit lines, main virtual groundlines, subordinate digit lines, and subordinate virtual ground lines amain digit line selector circuit being connected to the main digit linesfor selecting at least one of the main digit lines; a main virtualground selector circuit being connected to the main virtual ground linesfor selecting at least one of the main virtual ground lines; a referencecell region including a plurality Of reference banks, each havingreference memory cells, reference digit lines, reference Virtual groundlines, subordinate reference digit lines and subordinate referencevirtual ground lines ; a reference digit line selector circuit beingconnected to the reference digit lines for selecting at least one of thereference digit lines ; a reference virtual ground selector circuitbeing connected to the reference virtual ground lines for selecting atleast one of the reference virtual ground lines ; a bank selectingcircuit connected to the subordinate digit lines and the referencesubordinate digit lines for selecting at least one of the subordinatedigit lines and connecting the at least one subordinate digit line tothe main digit line, and further selecting at least one of thesubordinate reference digit lines and connecting the at least onesubordinate reference digit line to the reference digit line; and aground selecting circuit connected to the subordinate main virtualground lines and the subordinate reference virtual ground lines forselecting at least one of the subordinate main virtual ground lines andconnecting the at least one subordinate main virtual ground line to themain virtual ground line, and further selecting at least one of thesubordinate reference virtual ground lines and connecting the at leastone subordinate reference virtual ground line to the reference virtualground line, wherein the reference cell region has substantially thesame interconnection routine as the memory cell region.

[0061] This sixth aspect of the present invention has the samepreferable practicable modes described above in connection with thefirst aspect of the present invention.

[0062] A seventh aspect of the present invention is a semiconductormemory device comprising: a memory cell region including a plurality ofmain banks, each having memory cells, main digit lines, main virtualground lines, subordinate digit lines, and subordinate virtual groundlines; a main digit line selector circuit being connected to the maindigit lines for selecting at least one of the main digit lines ; a mainvirtual ground selector circuit being connected to the main virtualground lines for selecting at least one of the main virtual groundlines; a reference cell region including a plurality of reference banks,each having reference memory cells, reference digit lines, referencevirtual ground lines, subordinate reference digit lines and subordinatereference virtual ground lines ; a reference digit line selector circuitbeing connected to the reference digit lines for selecting at least oneof the reference digit lines ; a reference virtual ground selectorcircuit being connected to the reference virtual ground lines forselecting at least one of the reference virtual ground lines ; a bankselecting circuit connected to the subordinate digit lines and thereference subordinate digit lines for selecting at least one of thesubordinate digit lines and connecting the at least one subordinatedigit line to the main digit line, and further selecting at least one ofthe subordinate reference digit lines and connecting the at least onesubordinate reference digit line to the reference digit line and aground selecting circuit connected to the subordinate main virtualground lines and the subordinate reference virtual ground lines forselecting at least one of the subordinate main virtual ground lines andconnecting the at least one subordinate main virtual ground line to themain virtual ground line, and further selecting at least one of thesubordinate reference virtual ground lines and connecting the at leastone subordinate reference virtual ground line to the reference virtualground line, wherein in the reference cell region, adjacent referencecells to a selected reference cell to be referred are off-bit cells.

[0063] This seventh aspect of the present invention has the samepreferable practicable modes described above in connection with thefirst aspect of the present invention.

[0064] An eighth aspect of the present invention is a semiconductormemory device comprising: a memory cell region including a plurality ofmain banks, each having memory cells, main digit lines, main virtualground lines, subordinate digit lines, and subordinate virtual groundlines; a main digit line selector circuit being connected to the maindigit lines for selecting at least one of the main digit lines; a mainvirtual ground selector circuit being connected to the main virtualground lines for selecting at least one of the main virtual groundlines; a reference cell region including a plurality of reference banks,each having reference memory cells, reference digit lines, referencevirtual ground lines, subordinate reference digit lines and subordinatereference virtual ground lines; a reference digit line selector circuitbeing connected to the reference digit lines for selecting at least oneof the reference digit lines; a reference virtual ground selectorcircuit being connected to the reference virtual ground lines forselecting at least one of the reference virtual ground lines; a bankselecting circuit connected to the subordinate digit lines and thereference subordinate digit lines for selecting at least one of thesubordinate digit lines and connecting the at least one subordinatedigit line to the main digit line, and further selecting at least one ofthe subordinate reference digit lines and connecting the at least onesubordinate reference digit line to the reference digit line and aground selecting circuit connected to the subordinate main virtualground lines and the subordinate reference virtual ground lines forselecting at least one of the subordinate main virtual ground lines andconnecting the at least one subordinate main virtual ground line to themain virtual ground line, and further selecting at least one of thesubordinate reference virtual ground lines and connecting the at leastone subordinate reference virtual ground line to the reference virtualground line, wherein the memory cell region possesses a first currentroutine pattern through the main digit line to the main memory celldesignated in accordance with a address signal, and the reference cellregion possesses a second current routine pattern through the referencedigit line to the reference memory cell in accordance with the addresssignal, and wherein the first current routine pattern is alwaysidentical with the second current routine pattern upon designating anymemory cell addresses.

[0065] This eighth aspect of the present invention has the samepreferable practicable modes described above in connection with thefirst aspect of the present invention.

[0066] A ninth aspect of the present invention is a semiconductor memorydevice comprising a memory cell region including a plurality of mainbanks, each having memory cells, main digit lines, main virtual groundlines, subordinate digit lines, and subordinate virtual ground lines; amain digit line selector circuit being connected to the main digit linesfor selecting at least one of the main digit lines; a main virtualground selector circuit being connected to the main virtual ground linesfor selecting at least one of the main virtual ground lines ; areference cell region including a plurality of reference banks, eachhaving reference memory cells, reference digit lines, reference virtualground lines, subordinate reference digit lines and subordinatereference virtual ground lines ; a reference digit line selector circuitbeing connected to the reference digit lines for selecting at least oneof the reference digit lines; a reference virtual ground selectorcircuit being connected to the reference virtual ground lines forselecting at least one of the reference virtual ground lines ; a bankselecting circuit connected to the subordinate digit lines and thereference subordinate digit lines for selecting at least one of thesubordinate digit lines and connecting the at least one subordinatedigit line to the main digit line, and further selecting at least one ofthe subordinate reference digit lines and connecting the at least onesubordinate reference digit line to the reference digit line and aground selecting circuit connected to the subordinate main virtualground lines and the subordinate reference virtual ground lines forselecting at least one of the subordinate main virtual ground lines andconnecting the at least one subordinate main virtual ground line to themain virtual ground line, and further selecting at least one of thesubordinate reference virtual ground lines and connecting the at leastone subordinate reference virtual ground line to the reference virtualground line, wherein the reference cell region includes adjacent firstand second subordinate regions, and the first subordinate region havingeven number banks having ON-bit cells and odd number banks havingOFF-bit cells, and the second subordinate region having even numberbanks having OFF-bit cells and odd number banks having ON-bit cells.

[0067] This ninth aspect of the present invention has the samepreferable practicable modes described above in connection with thefirst aspect of the present invention.

[0068] A preferred embodiment according to the present invention will bedescribed in detail with reference to the drawings. FIG. 3 isillustrative of a semiconductor memory device of this first embodimentaccording to the present invention.

[0069] The semiconductor memory device includes a memory cell region 7which includes memory cell arrays. The memory cell region 7 furtherincludes main digit lines D, main virtual ground lines VG, bankselecting lines BS, word lines W, and ground selecting lines GS forselecting, in a bank unit, cell transistors in the memory cell arrays.

[0070] The semiconductor memory device may include an X-decoder 1 beingconnected to the bank selecting lines BS, the word lines W, and theground selecting lines GS of the memory cell region 7. The X-decoder 1receives address signals for decoding the same, so that in accordancewith the decoded signals, the X-decoder 1 selects one of the bankselecting lines BS, one of the word lines W, and one of the groundselecting lines GS.

[0071] The semiconductor memory device may include a Y-selector circuit2 being connected to the main digit lines D of the memory cell region 7.The semiconductor memory device may also include sense amplifiers SA0,SAX, which are connected to the Y-selector circuit 2. The semiconductormemory device may also include differential circuits DF0,---- DFX, whichare connected to the sense amplifiers SA0, ---- SAX, respectively. Thesemiconductor memory device may also include output stages OP0, -----OPX, which are connected to the differential circuits DF0, ---- DFX,respectively. The output stages OP0, ----- OPX are also connected tooutput terminals OUT0, -----OUTX.

[0072] The semiconductor memory device may also include a singlepre-charge circuit 3 which is connected to the Y-selector circuit 2. Thepre-charge circuit 3 applies a bias voltage to non selected memory cellsof the memory cell region 7 based on the selected memory cell.

[0073] The Y-selector circuit 2 receives another address signal forselecting plural pairs of the main digit lines D and connecting theselected pairs of the main digit lines D to the sense amplifiers SA0,---- SAX, and the pre-charge circuit 3.

[0074] The semiconductor memory device may also include a virtual groundline selector circuit 8 being connected to main virtual ground lines VGof the memory cell region 7. The virtual ground line selector circuit 8being connected to a ground line GND. The semiconductor memory devicemay also include a subordinate pre-charge circuit 10 which is connectedto the virtual ground line selector circuit 8. The subordinatepre-charge circuit 10 also supplies another bias voltage to non-selectedmemory cells of the memory cell region 7 based on the selected memorycell.

[0075] The virtual ground line selector circuit 8 receives still anotheraddress signal for selecting one of the main virtual ground lines VG andconnecting the selected one of the main virtual ground lines VG to theground line GNU and the subordinate pre-charge circuit 10.

[0076] The semiconductor memory device also includes a reference cellregion 6 which includes reference cell arrays. The reference cell region6 includes reference digit lines RD. The reference cell region 6generates a digit line reference signal to be used for read-out signalfor reading out storage informations from the memory cell region 7.

[0077] The semiconductor memory device may also include a dummyY-selector circuit 5 being connected to the reference digit lines RD ofthe reference cell region 6. The dummy Y-selector circuit 5 is alsoconnected to the pre-charge circuit 3. The semiconductor memory devicemay also include a reference amplifier 4 connected to the dummyY-selector circuit 5 and the differential circuits DF0, ---- DFX. Thedummy Y-selector circuit 5 receives yet another address signal forselecting one pair of the reference digit lines RD and connecting theselected one pair of the reference digit lines RD to the referenceamplifier 4 and the pre-charge circuit 3.

[0078] The semiconductor memory device may also include a dummy virtualground line selector circuit 9 being connected to the reference virtualground lines RVD of the reference cell region 6. The dummy virtualground line selector circuit 9 is also connected to the subordinatepre-charge circuit 10 and the ground line GND. The dummy virtual groundline selector circuit 9 receives further another address signal forselecting one of the reference virtual ground lines RVD of the referencecell region 6 and connecting the selected one reference virtual groundline RVD to the subordinate pre-charge circuit 10 and the ground lineGND.

[0079] Each of the sense amplifiers SA0, ---- SAX supplies a voltage tothe memory cell transistor of the memory cell region 7 through aY-selector transistor and a bank selector transistor. The referenceamplifier 4 may have the same interconnection routine as the senseamplifiers SA0, ----SAX. The reference amplifier 4 supplies a voltage tocell transistor of the reference cell region 6 through a dummy Y-cellselector transistor and a bank selector transistor.

[0080] The differential circuits DF0, ---- DFX receive sense amplifiercurrents ISA which are supplied to the memory cell transistors of thememory cell region 7 from the sense amplifiers SA0, ---- SAX. Thedifferential circuits DF0, ---- DFX also receive a reference current IRAwhich is supplied to the memory cell transistor of the reference cellregion 6 from the reference amplifier 4. The differential circuits DF0,---- DFX compare the sense amplifier currents ISA to the referencecurrent IRA for judging whether the selected cell is ON-bit cell orOFF-bit cell. The differential circuits DF0, ---- DFX output binarydigit data of “0” or “1” which indicate ON-bit cell or OFF-bit cell.Each of the differential circuits DF0, ---- DFX may generally have aratio as follows.

[0081] ON-bit cell “0”: ISA is larger than (IRA)/2

[0082] OFF-bit cell “1”: ISA is smaller than (IRA)/2

[0083] The output stages OP0, ---OPX receive ON-bit/OFF-bit outputsignals from the differential circuits DF0,---- DFX and amplify thesignals for outputting output signals OUT0, ---- OUTX.

[0084] The X-decoder 1, the sense amplifiers SA0, --- SAX, the referenceamplifier 4, the differential circuits DF0, ---- DFX, the output stagesOP0, ---- OPX, the pre-charge circuit 3, and the subordinate pre-chargecircuit 10 may be configured by the known circuit configurations.

[0085]FIG. 4 is a fragmentary circuit diagram of the memory cell regionhaving a flat-cell structure in the semiconductor device of FIG. 3. Thememory cell region 7 includes main digit lines Df, D0, D1, D2, D3, D4and DS which may comprise metal interconnections, and main virtualground lines VGf, VG0, VG1, VG2, VG3, VG4 and VG5 which may comprisemetal interconnections. The memory cell region 7 also includessubordinate digit lines SDf1, SD00, SD01, SD10, SD11, SD20, SD21, SD30,SD31, SD40, SD41, and SD150 which may comprise diffusion layers. Thememory cell region 7 also includes subordinate virtual ground linesSVGf0, SVG00, SVG01, SVG02, SVG03, SVG10, SVG11, SVG12, SVG13, SVG20,SVG21, SVG22, and SVG23.

[0086] The memory cell region 7 also includes word lines W00, W01, ---W0n. The memory cell region 7 also includes bank selecting lines BS0 andBS1. The memory cell region 7 also includes ground selecting lines GS0,GS1, GS2 and GS3.

[0087] The memory cell region 7 also includes bank selector transistorsTbf, Tb0, Tb1, Tb2, Tb3, Tb4, Tb5, Tb6, Tb7, Tb8, Tb9, and Tb10. Thebank selecting transistor Tbf is connected in series between the maindigit line Df and the subordinate digit line SDf1. The bank selectingtransistor Tb0 is connected in series between the main digit line D0 andthe subordinate digit line SD00. The bank selecting transistor Tb1 isconnected in series between the main digit line D0 and the subordinatedigit line SD01. The bank selecting transistor Tb2 is connected inseries between the main digit line D1 and the subordinate digit lineSD10. The bank selecting transistor Tb3 is connected in series betweenthe main digit line D1 and the subordinate digit line SD11. The bankselecting transistor Tb4 is connected in series between the main digitline D2 and the subordinate digit line SD20. The bank selectingtransistor Tb5 is connected in series between the main digit line D2 andthe subordinate digit line SD21. The bank selecting transistor Tb6 isconnected in series between the main digit line D3 and the subordinatedigit line SD30. The bank selecting transistor Tb7 is connected inseries between the main digit line D3 and the subordinate digit lineSD31. The bank selecting transistor Tb8 is connected in series betweenthe main digit line D4 and the subordinate digit line SD40. The bankselecting transistor Tb9 is connected in series between the main digitline D4 and the subordinate digit line SD41. The bank selectingtransistor Tb10 is connected in series between the main digit line D5and the subordinate digit line SD50.

[0088] The bank selecting line BS1 is connected to gates of the bankselector transistors Tbf, Tb1, Tb3, Tb5, Tb7 and Tb9. The bank selectingline BS0 is connected to gates of the bank selector transistors Tb0,Tb2, Tb4, Tb6, Tb8 and Tb10.

[0089] The memory cell region 7 also includes ground selectortransistors Tgf, Tg0, Tg1, Tg2, Tg3, Tg4, Tg5, Tg6, Tg7, Tg8, Tg9, Tg10and Tg11. The ground selecting transistor Tgf is connected in seriesbetween the main virtual ground line VGf and the subordinate virtualground line SVGf1. The ground selecting transistor Tg0 is connected inseries between the main virtual ground line VG0 and the subordinatevirtual ground line SVG00. The ground selecting transistor Tg1 isconnected in series between the main virtual ground line VG0 and thesubordinate virtual ground line SVG01. The ground selecting transistorTg2 is connected in series between the main virtual ground line VG0 andthe subordinate virtual ground line SVG02. The ground selectingtransistor Tg3 is connected in series between the main virtual groundline VG0 and the subordinate virtual ground line SVG03. The groundselecting transistor Tg4 is connected in series between the main virtualground line VG1 and the subordinate virtual ground line SVG10. Theground selecting transistor Tg5 is connected in series between the mainvirtual ground line VG1 and the subordinate virtual ground line SVG11.The ground selecting transistor Tg6 is connected in series between themain virtual ground line VG1 and the subordinate virtual ground lineSVG12. The ground selecting transistor Tg7 is connected in seriesbetween the main virtual ground line VG1 and the subordinate virtualground line SVG13. The ground selecting transistor Tg8 is connected inseries between the main virtual ground line VG2 and the subordinatevirtual ground line SVG20. The ground selecting transistor Tg9 isconnected in series between the main virtual ground line VG2 and thesubordinate virtual ground line SVG21. The ground selecting transistorTg10 is connected in series between the main virtual ground line VG2 andthe subordinate virtual ground line SVG22. The ground selectingtransistor Tg11 is connected in series between the main virtual groundline VG2 and the subordinate virtual ground line SVG23.

[0090] The ground selecting line GS0 is connected to gates of the groundselecting transistors Tg0, Tg4, and Tg8. The ground selecting line GS1is connected to gates of the ground selecting transistors Tg1, Tg5, andTg9. The ground selecting line GS2 is connected to gates of the groundselecting transistors Tg2, Tg6, and Tg10. The ground selecting line GS3is connected to gates of the ground selecting transistors Tgf, Tg3, Tg7,and Tg11.

[0091] The bank selecting lines BS0 and BS1 are connected to the gatesof the bank selector transistors Tbf, Tb0, Tb1, Tb2, Tb3, Tb4, Tb5, Tb6,Tb7, Tb8, Tb9, and Tb10 for selectively connecting the subordinate digitlines SDf1, SD00, SD01, SD10, SD11, SD20, SD21, SD30, SD31, SD40, SD41,and SD50 to the main digit lines Df, F0, D1, D2, D3, D4, and D5. Theground selecting lines GS0, GS1, GS2 and GS3 are connected to the gatesof the ground selector transistors Tgf, Tg0, Tg1, Tg2, Tg3, Tg4, Tg5,Tg6, Tg7, Tg8, Tg9, Tg10 and Tg11 for selectively connecting thesubordinate virtual ground lines SVGf0, SVG00, SVG01, SVG02, SVG03,SVG10, SVG11, SVG12, SVG13, SVG20, SVG21, SVG22, and SVG23 to the mainvirtual ground lines VGf, VG0, VG1, and VG2.

[0092] The memory cell region 7 also includes memory cell transistorswhich are connected in series between adjacent pairs of the subordinatedigit lines SDf1, SD00, SD01, SD10, SD11, SD20, SD21, SD30, SD31, SD40,SD41, and SD50 and the subordinate virtual ground lines SVGf0, SVG00,SVG01, SVG02, SVG03, SVG10, SVG11, SVG12, SVG13, SVG20, SVG21, SVG22,and SVG23.

[0093] A bank BANKf6 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVGf0, and thesubordinate digit line SDf1, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0094] A bank BANKf7 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG00, and thesubordinate digit line SDf1, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0095] A bank BANK00 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG00, and thesubordinate digit line SD00, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0096] A bank BANK01 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG01, and thesubordinate digit line SD00, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0097] A bank BANK02 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG01, and thesubordinate digit line SD01, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0098] A bank BANK03 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG02, and thesubordinate digit line SD01, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0099] A bank BANK04 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG12, and thesubordinate digit line SD10, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0100] A bank BANK05 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG03, and thesubordinate digit line SD10, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0101] A bank BANK06 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG03, and thesubordinate digit line SD11, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0102] A bank BANK07 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG10, and thesubordinate digit line SD11, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0103] The above eight banks BANK00, BANK01, BANK02, BANK03, BANK04,BANK05, BANK06, and BANK07 form a first unit. The number of the banksfor a single unit may optionally be decided in consideration of memorycapacity.

[0104] A bank BANK10 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG10, and thesubordinate digit line SD20, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0105] A bank BANK11 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG11, and thesubordinate digit line SD20, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0106] A bank BANK12 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG11, and thesubordinate digit line SD21, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0107] A bank BANK13 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG12, and thesubordinate digit line SD21, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0108] A bank BANK14 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG12, and thesubordinate digit line SD30, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0109] A bank BANK15 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG13, and thesubordinate digit line SD30, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0110] A bank BANK16 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG13, and thesubordinate digit line SD31, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0111] A bank BANK17 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG20, and thesubordinate digit line SD31, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0112] The above eight banks BANK10, BANK11, BANK12, BANK13, BANK14,BANK15, BANK16, and BANK17 form a second unit. The number of the banksfor a single unit may optionally be decided in consideration of memorycapacity.

[0113] A bank BANK20 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG20, and thesubordinate digit line SD40, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0114] A bank BANK21 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG21, and thesubordinate digit line SD40, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0115] A bank BANK22 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG21, and thesubordinate digit line SD41, wherein gates of the memory celltransistors ate respectively connected to the word lines W00, --- W0n.

[0116] A bank BANK23 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG22, and thesubordinate digit line SD41, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0117] A bank BANK24 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG22, and thesubordinate digit line SD50, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0118] A bank BANK25 has memory cell transistors which are connected inseries between the subordinate virtual ground line SVG23, and thesubordinate digit line SD50, wherein gates of the memory celltransistors are respectively connected to the word lines W00, --- W0n.

[0119]FIG. 5 is a fragmentary circuit diagram of the Y-selector circuitin the semiconductor memory device of FIG. 3. The Y-selector circuit 2include selecting signal lines Y0, Y1, Y2, Y3, PC0, PC1, PC2, and PC3,and transistors 30, 31, 32, 33, 34, 35, 36, 37, 70, 71, 72, 73, 74, and75. Drains of the transistors 30, 31, 32, and 33 are connected to thesense amplifier SA0. Drains of the transistors 70, 71, andnon-illustrated other transistors are connected to the sense amplifierSA1. A drain of the transistor 72 is connected to the sense amplifierSAf.

[0120] The selecting line Y0 is connected to gates of the transistors 30and 70. The selecting line Y1 is connected to gates of the transistors31 and 71. The selecting line Y2 is connected to gates of thetransistors 32 and 72. The selecting line Y3 is connected to gates ofthe transistors 33 and 73. A source of the transistor 30 is connected tothe main digit line D0. A source of the transistor 31 is connected tothe main digit line D1. A source of the transistor 32 is connected tothe main digit line D2. A source of the transistor 33 is connected tothe main digit line D3. A source of the transistor 70 is connected tothe main digit line D4. A source of the transistor 71 is connected tothe main digit line D5. A source of the transistor 72 is connected tothe main digit line Df.

[0121] Drains of the transistors 34, 35, 36, 37, 73, 74 and 75 areconnected to the pre-charge Circuit 3. The selecting line PC0 isconnected to gates of the transistors 34 and 73. The selecting line PC1is connected to gates of the transistors 35 and 74. The selecting linePC2 is connected to gate of the transistor 36. The selecting line PC3 isconnected to gates of the transistors 37 and 75. A source of thetransistor 34 is connected to the main digit line D0. A source of thetransistor 35 is connected to the main digit line D1. A source of thetransistor 36 is connected to the main digit line D2. A source of thetransistor 37 is connected to the main digit line D3. A source of thetransistor 73 is connected to the main digit line D4. A source of thetransistor 74 is connected to the main digit line D5.

[0122] The sense amplifiers are provided for every sixteen banks and thepre-charge circuit 3 is provided for all banks.

[0123]FIG. 6 is a fragmentary circuit diagram of the virtual groundselector circuit in the semiconductor memory device of FIG. 3. Thevirtual ground selector circuit 8 include selecting signal lines VGSf,VGS0, VGS1, VGS2, SPCf, SPC0, SPC1, and SPC2, and transistors 60, 61,62, 63, 64, 65, 80, and 81. The selecting signal line VGSf is connectedto a gate of the transistor 80. The selecting signal line VGS0 isconnected to a gate of the transistor 60. The selecting signal line VGS1is connected to a gate of the transistor 61. The selecting signal lineVGS2 is connected to a gate of the transistor 62. The selecting signalline SPCf is connected to a gate of the transistor 81. The selectingsignal line SPC0 is connected to a gate of the transistor 63. Theselecting signal line SPC1 is connected to a gate of the transistor 64.The selecting signal line SPC3 is connected to a gate of the transistor65.

[0124] Drains of the transistors 80 and 81 are connected to the mainvirtual ground line VGf. Drains of the transistors 60 and 63 areconnected to the main virtual ground line VG0. Drains of the transistors61 and 64 are connected to the main virtual ground line VG1. Drains ofthe transistors 62 and 65 are connected to the main virtual ground lineVG2. Sources of the transistors 60, 61, 62 and 81 are connected to theground line GND. Sources of the transistors 63, 64, 65 and 80 areconnected to the subordinate pre-charge circuit 10.

[0125]FIG. 7 is a table of truth values for selecting banks of thememory cell region in the semiconductor memory device of FIG. 3, whereinmark “H” means high level, and no mark means low level. The tabledescribes the banks BANK00, --- BANK07, and BANK 10, --- BANK17. Thetruth values of those banks are common to further banks BANK20, ---BANK27, and BANK 30, --- BANK 37, and to further more banks BANK2n0, --BANK2n7, and BANK (2n+1)0, --- BANK (2n+1)7.

[0126] Operations of the memory cells will be described if a memory celltransistor “A” (BANK02, word W00) is selected in the memory cell region7. The bank selecting line BS1 and the ground selecting line GS1 arehigh level. The Y-selector circuit 2 places the selecting signal linesY0 and PC1 in high level. The virtual ground selector circuit places theselecting signal lines VGS0 and SPC1 in high level.

[0127] The bank selecting line BS1 in high level turns the bank selectortransistors Tb1, Tb3, Tb5 and Tb7 ON. The ground selecting line in highlevel also turns the ground selector transistors Tg1 and Tg5 ON. Theselecting signal line VGS0 in high level turns the transistor 60 ON,whereby the main virtual ground line VG0 is connected to the ground lineGND by the virtual ground selector circuit 8. The selecting signal lineSPC1 in high level turns the transistor 64 ON, whereby the main virtualground line VG1 is connected to the subordinate pre-charge circuit 10 bythe virtual ground selector circuit 8.

[0128] As a result, the main digit line D0 has a first current path tothe ground line GND, wherein the first current path includes the bankselector transistor Tb1, the memory cell transistor “A”, the groundselector transistor Tg1, the main virtual ground line VG0, thetransistor 60 of the virtual ground selector circuit 8, and the groundline GND. The main digit line D1 has a second current path to thesubordinate pre-charge circuit 10, wherein the second current pathincludes the bank selector transistor Tb5, the memory cell transistor“A′”, the ground selector transistor Tg5, the main virtual ground lineVG1, the transistor 64 of the virtual ground selector circuit 8, and thesubordinate pre-charge circuit 10. At this time, in the Y-selectorcircuit 2, the selecting line Y0 is in high level, and the selectingline Y0 turns the transistor 30 ON, whereby the main digit line D0 isconnected to the sense amplifier SA0. The selecting line PC1 is notselected, whereby the memory cell “A′” is not applied with the voltagefrom the sense amplifier SA0. The memory cell “A” is ON-bit cell, and acurrent including information flows onto the main digit line D2, wherebythe information is read out.

[0129] The main digit line D1 is connected to the pre-charge circuit 3,whereby a pre-charge voltage is supplied from the pre-charge circuit 3through the bank selector transistor Tb3 to the cell transistors 03, 04,05 and 06. This pre-charge voltage has the same voltage as the biasvoltage supplied from the sense amplifier SA0. If the memory cell “A” isOFF-bit cell, the sources and drains of the memory cell transistors inthe banks BANK03, BANK04, BANK05, and BANK06 have the same potential,whereby a read-out current is not applied to the memory cell transistorsin the banks BANK03, BANK04, BANK05, and BANK06, and it is correctlyrecognized that the memory cell “A” is OFF-bit cell.

[0130] The main virtual GND line VG1 is connected to the subordinatepre-charge circuit 10. Similarly to operations of the pre-chargescircuit 3, the charge voltage is applied from the subordinate pre-chargecircuit 10 through the ground selector transistor Tg5 to the memory celltransistors in the banks BANK11, and BANK12. In this example, memorycells in both sides are OFF-bit cells, for which reason the voltage fromthe pre-charge circuit 3 is not supplied to other devices. Assuming thatall of the memory cells are ON-bit cells, the capacity of the pre-chargecircuit 3 might be insufficient, and the subordinate pre-charge circuit10 is provided for supplementing the current.

[0131]FIG. 8 is a circuit diagram of the reference cell region of thesemiconductor memory device of FIG. 3. The reference cell region 6 hassubstantially the same interconnection routines as the memory cellregion 7 which has been described above with reference to FIG. 4. Thereference cell region 6 shows substantially the same operations as thememory cell region 7 which has been described above.

[0132] Reference digit lines RD0, RD1, RD2, and RD3 of the referencecell region 6 correspond to the above main digit lines D0, D1, D2, andD3 of the memory cell region 7. Bank selector transistors Trb0, Trb1,Trb2, Trb3, Trb4, Trb5, Trb6 and Trb7 of the reference cell region 6correspond to the above bank selector transistors Tb0, Tb1, Tb2, Tb3,Tb4, Tb5, Tb6 and Tb7 of the memory cell region 7. Ground selectortransistors Trg0, Trg1, Trg2, Trg3, Trg4, Trg5, Trg6, and Trg7 of thereference cell region 6 correspond to the above ground selectortransistors Tg0, Tg1, Tg2, Tg3, Tg4, Tg5, Tg6, and Tg7 of the memorycell region 7. Reference virtual ground lines RVG0, RVG1, and RVG2 ofthe reference cell region 6 correspond to the above main virtual groundlines VG0, VG1, and VG2 of the memory cell region 7.

[0133] In the reference cell region 6, cell transistors in adjacent twobanks to a cell transistor to be referred are off-bit cells. Thereference cell region 6 has sixteen banks classified into first andsecond eight-bank units. The first eight-bank unit comprises four evennumber banks BANK0, BANK2, BANK4 and BANK6 which are ON-bit cells, andfour odd number banks BANK1, BANK3, BANK5 and BANK7 which are OFF-bitcells. The second eight-bank unit comprises four even number banksBANK0, BANK2, BANK4 and BANK6 which are OFF-bit cells, and four oddnumber banks BANK1, BANK3, BANKS and BANK7 which are ON-bit cells. Theword lines, the bank selecting lines and the ground selecting lines inthe reference cell region 6 are common to the memory cell region 7.

[0134]FIG. 9 is a circuit diagram of the dummy Y-selector circuit of thesemiconductor memory device of FIG. 3. The dummy Y-selector circuit 5has substantially the same interconnection routine as the Y-selectorcircuit 2 which has been described above with reference to FIG. 5. Thedummy Y-selector circuit 5 exhibits substantially the same operations asthe Y-selector circuit 2 which has been described above. Selectingsignal lines DY0, DY1, DY2, and DY3 of the dummy Y-selector circuit 5correspond to the above selecting signal lines Y0, Y1, Y2, and Y3 of theY-selector circuit 2. Selecting signal lines DPC0, DPC1, DPC2 and DPC3of the dummy Y-selector circuit 5 correspond to the above selectingsignal lines PC0, PC1, PC2 and PC3 of the Y-selector circuit 2.Transistors 40, 41, 42, 43, 44, 45, 46, and 47 of the dummy Y-selectorcircuit 5 correspond to the above transistors 30, 31, 32, 33, 34, 35,36, and 37 of the Y-selector circuit 2. Reference digit lines RD0, RD1,RD2 and RD3 of the dummy Y-selector circuit 5 correspond to the abovemain digit lines D0, D1, D2 and D3 of the Y-selector circuit 2.

[0135]FIG. 10 is a circuit diagram of the dummy virtual ground selectorcircuit of the semiconductor memory device of FIG. 3. The dummy virtualground selector circuit 9 has substantially the same interconnectionroutine as the virtual ground selector circuit 8 which has beendescribed above with reference to FIG. 6. The dummy virtual groundselector circuit 9 also exhibits substantially the same operations asthe virtual ground selector circuit 8 which has been described above.Selecting signal lines DVGS0, DVGS1, and DVGS2 of the dummy virtualground selector circuit 9 correspond to the above selecting signal linesVGS0, VGS1, and VGS2 of the virtual ground selector circuit 8. Selectingsignal lines DSPC0, DSPC1, and DSPC2 of the dummy virtual groundselector circuit 9 correspond to the above selecting signal lines SPC0,SPC1, and SPC2 of the virtual ground selector circuit 8. Transistors 50,51, 52, 53, 54 and 55 of the of the dummy virtual ground selectorcircuit 9 correspond to the above transistors 60, 61, 62, 63, 64, and 65of the virtual ground selector circuit 8. Reference virtual ground linesRVG0, RVG1, and RVG2 of the of the dummy virtual ground selector circuit9 correspond to the above main virtual ground lines VG0, VG1, and VG2 ofthe virtual ground selector circuit 8.

[0136] The selecting signals to the dummy Y-selector 5 and the dummyvirtual ground selector 9 are independent from the selecting signals ofthe memory cell region 7. The above selecting signals to the dummyY-selector 5 and the dummy virtual ground selector 9 are decideddepending on which bank of the memory cell region is selected.

[0137]FIG. 11 is a table of truth values for selecting banks of thereference cell region in the semiconductor memory device of FIG. 3,wherein mark “H” means high level, and no mark means low level. Thetable describes the banks BANK00, --- BANK07. Operations of thereference cell region 6 are substantially the same as the memory cellregion 7. Operations of the memory cells in the memory cell region 7upon selecting the BANK00 and the BANK10 on table 7 are identical withoperations of the reference cells in the memory cell region 6 uponselecting the BANK00 on table 11. Operations of the memory cells in thememory cell region 7 upon selecting the BANK01 and the BANK11 on table 7are identical with operations of the reference cells in the memory cellregion 6 upon selecting the BANK01 on table 11. Operations of the memorycells in the memory cell region 7 upon selecting the BANK02 and theBANK12 on table 7 are identical with operations of the reference cellsin the memory cell region 6 upon selecting the BANK02 on table 11.Operations of the memory cells in the memory cell region 7 uponselecting the BANK03 and the BANK13 on table 7 are identical withoperations of the reference cells in the memory cell region 6 uponselecting the BANK03 on table 11. Operations of the memory cells in thememory cell region 7 upon selecting the BANK04 and the BANK14 on table 7are identical with operations of the reference cells in the memory cellregion 6 upon selecting the BANK04 on table 11. Operations of the memorycells in the memory cell region 7 upon selecting the BANK05 and theBANK15 on table 7 are identical with operations of the reference cellsin the memory cell region 6 upon selecting the BANK05 on table 11.Operations of the memory cells in the memory cell region 7 uponselecting the BANK06 and the BANK16 on table 7 are identical withoperations of the reference cells in the memory cell region 6 uponselecting the BANK06 on table 11, Operations of the memory cells in thememory cell region 7 upon selecting the BANK07 and the BANK17 on table 7are identical with operations of the reference cells in the memory cellregion 6 upon selecting the BANK07 on table 11.

[0138] As described above, operations of the reference cell region 6 aresubstantially the same as the memory cell region 7. A current route ismade from the reference amplifier 4 through the transistor 40 of thedummy Y-selector circuit, the reference digit line RD0, the bankselector transistor Trb1, the reference cell B, the ground selectortransistor Trg1, the reference virtual ground line RVG0, the transistor50 of the dummy virtual ground selector circuit 9 to the ground lineGND, whereby stored information in the reference cell B is read out.

[0139]FIG. 12 is a view of respective positional inter-relationshipsbetween main digit lines and main virtual ground lines for variousbanks. The main digit lines are displaced upwardly. The main virtualground lines are displaced downwardly. Eight types of the positionalinter-relationships are illustrated for the eight banks BANK10, BANK11,BANK12, BANK13, BANK14, BANK15, BANK16, and BANK17. In the banks BANK11,BANK13, BANK14 and BANK16, the main digit lines respectively connectedto the pre-charge circuit “PC” and the sense amplifier “SA” are adjacentto each other.

[0140]FIG. 13 is a diagram of time-variations in voltage of the selecteddigit lines upon selecting the respective eight banks, wherein the cellfor read out object is ON-bit cell. In the banks BANK11, BANK13, BANK14and BANK16, the voltage rising speed is highest because the digit lineconnected to the pre-charge circuit is closer to the digit lineconnected to the sense amplifier, and thus a charge current from thesense amplifier for charging up the pre-charge circuit is small.

[0141] If a bank of the memory cell region is selected, then the bank ofthe reference cell region having the same structure is always selected.Even the charge-up speed of the main digit line is different betweendifferent banks due to parasitic capacitances between interconnections.The charge-up speed of the main digit line in the memory cell region 7is identical with the charge-up speed of the reference digit line in thereference cell region 6. The semiconductor memory device is free of anybank column dependency in read-out operation.

[0142]FIG. 14A is a diagram of time-dependent variations in senseamplifier currents ISA from the sense amplifiers and in reference senseamplifier currents IRA from the reference sense amplifiers when a mainmemory cell “A” is selected, wherein adjacent cells are ON-bit cells.FIG. 14B is a diagram of time-dependent variations in sense amplifiercurrents ISA from the sense amplifiers and in reference sense amplifiercurrents IRA from the reference sense amplifiers when another mainmemory cell “A′” is selected, wherein adjacent cells are OFF-bit cells.In either case of selecting the memory cells “A” and “A′”, then thereference cell “B” on the even number bank is selected. The senseamplifier current ISA upon selecting the memory cell “A”, adjacent toON-bit cells, are compared with the sense amplifier current ISA′ uponselecting the memory cell “A′”, adjacent to OFF-bit cells. Thesubordinate virtual ground lines SVG02 are charged-up through theadjacent cells. The sense amplifier current ISA upon selecting thememory cell “A” become temporary higher than the sense amplifier currentISA′ upon selecting the memory cell “A′”. Since, however, the senseamplifier current ISA is larger than the reference sense amplifiercircuit IRA, the differential circuit may rapidly judge the ON-bit cellimmediately after application of the sense amplifier current to thecells is started.

[0143] In the reference cell region, adjacent cells to the selectedreference cell are always OFF-bit cells, whereby no capacitance isprovided to the reference current route. Accordingly, in case ofselecting the memory cell “A′” adjacent to two OFF-bit cells, thereference sense amplifier current is equal to the sense amplifiercurrent ISA′ to the sense amplifier current. The differential circuitmay rapidly judge the ON-bit cell immediately after application of thesense amplifier current ISA′ to the cells is started.

[0144] The reference cell region 6 has the same configuration as thememory cell region 7, so that the properties of the reference digitlines are decided to follow to the change of addresses of the memorycell region 7, thereby avoiding the bank-dependency.

[0145] Cells transistors in the adjacent banks to the designated bankare OFF-bit cells to eliminate any substantive influence of thecapacitance added to the current path for avoiding the code-patterndependency.

[0146] Although the invention has been described above in connectionwith several preferred embodiments therefor, it will be appreciated thatthose embodiments have been provided solely for illustrating theinvention, and not in a limiting sense. Numerous modifications andsubstitutions of equivalent materials and techniques will be readilyapparent to those skilled in the art after reading the presentapplication, and all such modifications and substitutions are expresslyunderstood to fall within the true scope and spirit of the appendedclaims.

What is claimed is:
 1. A semiconductor memory device including: a memorycell region including main memory cells, main digit lines, and mainvirtual ground lines, and said memory cell region possessing a firstcurrent routine pattern through said main digit line to said main memorycell designated in accordance with a address signal; and a referencecell region including reference memory cells, reference digit lines, andreference virtual ground lines, and said reference cell regionpossessing a second current routine pattern through said reference digitline to said reference memory cell in accordance with said addresssignal, wherein said first current routine pattern is always identicalwith said second current routine pattern upon designating any memorycell addresses.
 2. The semiconductor memory device as claimed in claim 1, further comprising a current detecting circuit, and wherein saidmemory cell region includes main virtual ground lines and main digitlines, at least first one of said main digit lines is selectivelyconnected to said current detecting circuit, at least first one of saidmain virtual ground lines is selectively connected to a ground line, andsaid at least first one main digit line connected to said currentdetecting circuit and said at least first one main virtual ground lineconnected to said ground line form a first main current route, whereinsaid reference cell region further includes reference digit lines, atleast first one of said reference digit lines is selectively connectedto said current detecting circuit, at least first one of said referencevirtual ground lines is selectively connected to said ground line, andsaid at least first one reference digit line connected to said currentdetecting circuit and said at least first one reference virtual groundline connected to said ground line form a first reference current route,which is identical with said first main current route.
 3. Thesemiconductor memory device as claimed in claim 2 , further comprising:a main digit line selector circuit for selecting at least one of saidmain digit lines, so that said selected at least one main digit line isconnected to said current detecting circuit; and a reference digit lineselector circuit for selecting at least one of said reference digitlines, so that said selected at least one reference digit line is alsoconnected to said current detecting circuit.
 4. The semiconductor memorydevice as claimed in claim 2 , further comprising: a main virtual groundline selector circuit for selecting at least one of said main virtualaround lines, so that said selected at least one main virtual groundline is connected to a ground line; and a reference virtual groundselector circuit for selecting at least one of said reference virtualground lines, so that said selected at least one reference virtualground line is also connected to said ground line.
 5. The semiconductormemory device as claimed in claim 2 , wherein said memory cell regionfurther includes subordinate memory digit lines, and said reference cellregion further includes subordinate reference digit lines, and furthercomprising a bank selecting circuit for selecting at least one of saidsubordinate memory digit lines, so that said selected at least onesubordinate memory digit line is connected to said main digit line, andfurther selecting at least one of said subordinate reference digitlines, so that said selected at least one subordinate reference digitline is connected to said reference digit line.
 6. The semiconductormemory device as claimed in claim 2 , further comprising a mainpre-charge circuit, and wherein at least second one of said main digitlines is selected and connected to said main pre-charge circuit, whereinsaid at least first one main digit line connected to said currentdetecting circuit, said at least second one of said main digit lineconnected to said main pre-charge circuit, and said at least first onemain virtual ground line connected to said ground line form a secondmain current route, wherein at least second one of said reference digitlines is selected and connected to said main pre-charge circuit, whereinsaid at least first one reference digit line connected to said currentdetecting circuit, said at least second one reference digit lineconnected to said main pre-charge circuit, and said at least first onereference virtual ground line connected to said ground line form a firstreference current route, which is identical with said first main currentroute.
 7. The semiconductor memory device as claimed in claim 6 ,further comprising a subordinate pre-charge circuit, and wherein atleast second one of said main virtual ground lines is selected andconnected to said subordinate pre-charge circuit, wherein said at leastfirst one main digit line connected to said current detecting circuit,said at least second one of said main digit line connected to saidsubordinate pre-charge circuit, said at least first one main virtualground line connected to said ground line, and said second one mainvirtual ground line form a third main current route, wherein at leastsecond one of said reference virtual ground lines is selected andconnected to said subordinate pre-charge circuit, and wherein said atleast first one reference digit line connected to said current detectingcircuit, said at least second one reference digit line connected to saidsubordinate pre-charge circuit, said at least first one referencevirtual ground line connected to said ground line, and said at leastsecond one reference virtual ground line form a fourth reference currentroute, which is identical with said third main current route.
 8. Thesemiconductor memory device as claimed in claim 2 , further comprising:subordinate memory digit lines in said memory cell region; subordinatereference digit lines in said reference cell region and at least a bankselecting circuit for selecting at least one of said subordinate memorydigit lines and connecting said selected at least one subordinate memorydigit line to said main digit line, as well as for selecting at leastone of said subordinate reference digit lines and connecting saidselected at least one subordinate reference digit line to said referencedigit line.
 9. The semiconductor memory device as claimed in claim 1 ,wherein, in said reference cell region, adjacent reference cells to aselected reference cell to be referred are off-bit cells.
 10. Thesemiconductor memory device as claimed in claim 1 , wherein saidreference cell region includes adjacent first and second subordinateregions, and said first subordinate region having even number bankshaving ON-bit cells and odd number banks having OFF-bit cells, and saidsecond subordinate region having even number banks having OFF-bit cellsand odd number banks having ON-bit cells.
 11. A semiconductor memorydevice including: a memory cell region having main virtual ground lines; and a reference cell region having reference virtual ground lines, andsaid reference cell region having substantially the same interconnectionroutine as said memory cell region, wherein, in said reference cellregion, adjacent reference cells to a selected reference cell to bereferred are off-bit cells.
 12. The semiconductor memory device asclaimed in claim 11 , further comprising a current detecting circuit,and wherein said memory cell region further includes main digit lines,at least first one of said main digit lines is selectively connected tosaid current detecting circuit, at least first one of said main virtualground lines is selectively connected to a ground line, and said atleast first one main digit line connected to said current detectingcircuit and said at least first one main virtual ground line connectedto said ground line form a first main current route, wherein saidreference cell region further includes reference digit lines, at leastfirst one of said reference digit lines is selectively connected to saidcurrent detecting circuit, at least first one of said reference virtualground lines is selectively connected to said ground line, and said atleast first one reference digit line connected to said current detectingcircuit and said at least first one reference virtual ground lineconnected to said ground line form a first reference current route,which is identical with said first main current route.
 13. Thesemiconductor memory device as claimed in claim 12 , further comprising:a main digit line selector circuit for selecting at least one of saidmain digit lines, so that said selected at least one main digit line isconnected to said current detecting circuit; and a reference digit lineselector circuit for selecting at least one of said reference digitlines, so that said selected at least one reference digit line is alsoconnected to said current detecting circuit.
 14. The semiconductormemory device as claimed in claim 12 , further comprising: a mainvirtual ground line selector circuit for selecting at least one of saidmain virtual ground lines, so that said selected at least one mainvirtual ground line is connected to a ground line; and a referencevirtual ground selector circuit for selecting at least one of saidreference virtual ground lines, so that said selected at least onereference virtual ground line is also connected to said ground line. 15.The semiconductor memory device as claimed in claim 12 , wherein saidmemory cell region further includes subordinate memory digit lines, andsaid reference cell region further includes subordinate reference digitlines, and further comprising a bank selecting circuit for selecting atleast one of said subordinate memory digit lines, so that said selectedat least one subordinate memory digit line is connected to said maindigit line, and further selecting at least one of said subordinatereference digit lines, so that said selected at least one subordinatereference digit line is connected to said reference digit line.
 16. Thesemiconductor memory device as claimed in claim 12 , further comprisinga main pre-charge circuit, and wherein at least second one of said maindigit lines is selected and connected to said main pre-charge circuit,wherein said at least first one main digit line connected to saidcurrent detecting circuit, said at least second one of said main digitline connected to said main pre-charge circuit, and said at least firstone main virtual ground line connected to said ground line form a secondmain current route, wherein at least second one of said reference digitlines is selected and connected to said main pre-charge circuit, whereinsaid at least first one reference digit line connected to said currentdetecting circuit, said at least second one reference digit lineconnected to said main pre-charge circuit, and said at least first onereference virtual ground line connected to said ground line form a firstreference current route, which is identical with said first main currentroute.
 17. The semiconductor memory device as claimed in claim 16 ,further comprising a subordinate pre-charge circuit, and wherein atleast second one of said main virtual ground lines is selected andconnected to said subordinate pre-charge circuit, wherein said at leastfirst one main digit line connected to said current detecting circuit,said at least second one of said main digit line connected to saidsubordinate pre-charge circuit, said at least first one main virtualground line connected to said ground line, and said second one mainvirtual ground line form a third main current route, wherein at leastsecond one of said reference virtual ground lines is selected andconnected to said subordinate pre-charge circuit, and wherein said atleast first one reference digit line connected to said current detectingcircuit, said at least second one reference digit line connected to saidsubordinate pre-charge circuit, said at least first one referencevirtual ground line connected to said ground line, and said at leastsecond one reference virtual ground line form a fourth reference currentroute, which is identical with said third main current route.
 18. Thesemiconductor memory device as claimed in claim 12 , further comprising:subordinate memory digit lines in said memory cell region; subordinatereference digit lines in said reference cell region and at least a bankselecting circuit for selecting at least one of said subordinate memorydigit lines and connecting said selected at least one subordinate memorydigit line to said main digit line, as well as for selecting at leastone of said subordinate reference digit lines and connecting saidselected at least one subordinate reference digit line to said referencedigit line.
 19. The semiconductor memory device as claimed in claim 11 ,wherein said reference cell region includes adjacent first and secondsubordinate regions, and said first subordinate region having evennumber banks having ON-bit cells and odd number banks having OFF-bitcells, and said second subordinate region having even number bankshaving OFF-bit cells and odd number banks having ON-bit cells.
 20. Asemiconductor memory device including: a memory cell region having maindigit lines and main virtual ground lines ; and a reference cell regionhaving reference digit lines and reference virtual ground lines, andsaid reference cell region having substantially the same interconnectionroutine as said memory cell region, a current detecting circuit; a maindigit line selector circuit for selecting at least one of said maindigit lines, so that said selected at least one main digit line isconnected to said current detecting circuit; and a reference digit lineselector circuit for selecting at least one of said reference digitlines, so that said selected at least one reference digit line is alsoconnected to said current detecting circuit; a main virtual ground lineselector circuit for selecting at least one of said main virtual groundlines, so that said selected at least one main virtual ground line isconnected to a ground line; a reference virtual ground selector circuitfor selecting at least one of said reference virtual ground lines, sothat said selected at least one reference virtual ground line is alsoconnected to said ground line; wherein said at least first one maindigit line connected to said current detecting circuit and said at leastfirst one main virtual ground line connected to said ground line form afirst main current route, and wherein said at least first one referencedigit line connected to said current detecting circuit and said at leastfirst one reference virtual ground line connected to said ground lineform a first reference current route, which is identical with said firstmain current route.
 21. The semiconductor memory device as claimed inclaim 20 , wherein, in said reference cell region, adjacent referencecells to a selected reference cell to be referred are off-bit cells. 22.The semiconductor memory device as claimed in claim 20 , wherein saidmemory cell region further includes subordinate memory digit lines, andsaid reference cell region further includes subordinate reference digitlines, and further comprising a bank selecting circuit for selecting atleast one of said subordinate memory digit lines, so that said selectedat least one subordinate memory digit line is connected to said maindigit line, and further selecting at least one of said subordinatereference digit lines, so that said selected at least one subordinatereference digit line is connected to said reference digit line.
 23. Thesemiconductor memory device as claimed in claim 20 , further comprisinga main pre-charge circuit, and wherein at least second one of said maindigit lines is selected and connected to said main pre-charge circuit,wherein said at least first one main digit line connected to saidcurrent detecting circuit, said at least second one of said main digitline connected to said main pre-charge circuit, and said at least firstone main virtual ground line connected to said ground line form a secondmain current route, wherein at least second one of said reference digitlines is selected and connected to said main pre-charge circuit, whereinsaid at least first one reference digit line connected to said currentdetecting circuit, said at least second one reference digit lineconnected to said main pre-charge circuit, and said at least first onereference virtual ground line connected to said ground line form a firstreference current route, which is identical with said first main currentroute.
 24. The semiconductor memory device as claimed in claim 23 ,further comprising a subordinate pre-charge circuit, and wherein atleast second one of said main virtual ground lines is selected andconnected to said subordinate pre-charge circuit, wherein said at leastfirst one main digit line connected to said current detecting circuit,said at least second one of said main digit line connected to saidsubordinate pre-charge circuit, said at least first one main virtualground line connected to said ground line, and said second one mainvirtual ground line form a third main current route, wherein at leastsecond one of said reference virtual ground lines is selected andconnected to said subordinate pre-charge circuit, and wherein said atleast first one reference digit line connected to said current detectingcircuit, said at least second one reference digit line connected to saidsubordinate pre-charge circuit, said at least first one referencevirtual ground line connected to said ground line, and said at leastsecond one reference virtual ground line form a fourth reference currentroute, which is identical with said third main current route.
 25. Thesemiconductor memory device as claimed in claim 20 , further comprising:subordinate memory digit lines in said memory cell region; subordinatereference digit lines in said reference cell region and at least a bankselecting circuit for selecting at least one of said subordinate memorydigit lines and connecting said selected at least one subordinate memorydigit line to said main digit line, as well as for selecting at leastone of said subordinate reference digit lines and connecting saidselected at least one subordinate reference digit line to said referencedigit line.
 26. The semiconductor memory device as claimed in claim 20 ,wherein said reference cell region includes adjacent first and secondsubordinate regions, and said first subordinate region having evennumber banks having ON-bit cells and odd number banks having OFF-bitcells, and said second subordinate region having even number bankshaving OFF-bit cells and odd number banks having ON-bit cells.
 27. Asemiconductor memory device including: a memory cell region having maindigit lines, main virtual ground lines, and subordinate memory digitlines; and a reference cell region having reference digit lines,reference virtual ground lines, and subordinate reference digit lines,and said reference cell region having substantially the sameinterconnection routine as said memory cell region, wherein adjacentreference cells to a selected reference cell to be referred are off-bitcells, at least a bank selecting circuit for selecting at least one ofsaid subordinate memory digit lines and connecting said selected atleast one subordinate memory digit line to said main digit line, as wellas for selecting at least one of said subordinate reference digit linesand connecting said selected at least one subordinate reference digitline to said reference digit line; a current detecting circuit; a maindigit line selector circuit for selecting at least one of said maindigit lines, so that said selected at least one main digit line isconnected to said current detecting circuit; a reference digit lineselector circuit for selecting at least one of said reference digitlines, so that said selected at least one reference digit line is alsoconnected to said current detecting circuit; a main virtual ground lineselector circuit for selecting at least one of said main virtual groundlines, so that said selected at least one main virtual ground line isconnected to a ground line; and a reference virtual ground selectorcircuit for selecting at least one of said reference virtual groundlines, so that said selected at least one reference virtual ground lineis also connected to said ground line, wherein said at least first onemain digit line connected to said current detecting circuit and said atleast first one main virtual ground line connected to said ground lineform a first main current route, and wherein said at least first onereference digit line connected to said current detecting circuit andsaid at least first one reference virtual ground line connected to saidground line form a first reference current route, which is identicalwith said first main current route.
 28. The semiconductor memory deviceas claimed in claim 27 , further comprising a main pre-charge circuit,and wherein at least second one of said main digit lines is selected andconnected to said main pre-charge circuit, wherein said at least firstone main digit line connected to said current detecting circuit, said atleast second one of said main digit line connected to said mainpre-charge circuit, and said at least first one main virtual ground lineconnected to said ground line form a second main current route, whereinat least second one of said reference digit lines is selected andconnected to said main pre-charge circuit, wherein said at least firstone reference digit line connected to said current detecting circuit,said at least second one reference digit line connected to said mainpre-charge circuit, and said at least first one reference virtual groundline connected to said ground line form a first reference current route,which is identical with said first main current route.
 29. Thesemiconductor memory device as claimed in claim 28 , further comprisinga subordinate pre-charge circuit, and wherein at least second one ofsaid main virtual ground lines is selected and connected to saidsubordinate pre-charge circuit, wherein said at least first one maindigit line connected to said current detecting circuit, said at leastsecond one of said main digit line connected to said subordinatepre-charge circuit, said at least first one main virtual ground lineconnected to said ground line, and said second one main virtual groundline form a third main current route, wherein at least second one ofsaid reference virtual ground lines is selected and connected to saidsubordinate pre-charge circuit, and wherein said at least first onereference digit line connected to said current detecting circuit, saidat least second one reference digit line connected to said subordinatepre-charge circuit, said at least first one reference virtual groundline connected to said ground line, and said at least second onereference virtual ground line form a fourth reference current route,which is identical with said third main current route.
 30. Thesemiconductor memory device as claimed in claim 27 , wherein saidreference cell region includes adjacent first and second subordinateregions, and said first subordinate region having even number bankshaving ON-bit cells and odd number banks having OFF-bit cells, and saidsecond subordinate region having even number banks having OFF-bit cellsand odd number banks having ON-bit cells.
 31. A semiconductor memorydevice including: a memory cell region having main virtual ground lines;and a reference cell region having reference virtual ground lines, andsaid reference cell region having substantially the same interconnectionroutine as said memory cell region, wherein said reference cell regionincludes adjacent first and second subordinate regions, and said firstsubordinate region having even number banks having ON-bit cells and oddnumber banks having OFF-bit cells, and said second subordinate regionhaving even number banks having OFF-bit cells and odd number bankshaving ON-bit cells.
 32. The semiconductor memory device as claimed inclaim 31 , wherein, in said reference cell region, adjacent referencecells to a selected reference cell to be referred are off-bit cells. 33.The semiconductor memory device as claimed in claim 31 , furthercomprising a current detecting circuit, and wherein said memory cellregion further includes main digit lines, at least first one of saidmain digit lines is selectively connected to said current detectingcircuit, at least first one of said main virtual ground lines isselectively connected to a ground line, and said at least first one maindigit line connected to said current detecting circuit and said at leastfirst one main virtual ground line connected to said ground line form afirst main current route, wherein said reference cell region furtherincludes reference digit lines, at least first one of said referencedigit lines is selectively connected to said current detecting circuit,at least first one of said reference virtual ground lines is selectivelyconnected to said ground line, and said at least first one referencedigit line connected to said current detecting circuit and said at leastfirst one reference virtual ground line connected to said ground lineform a first reference current route, which is identical with said firstmain current route.
 34. The semiconductor memory device as claimed inclaim 33 , further comprising: a main digit line selector circuit forselecting at least one of said main digit lines, so that said selectedat least one main digit line is connected to said current detectingcircuit; and a reference digit line selector circuit for selecting atleast one of said reference digit lines, so that said selected at leastone reference digit line is also connected to said current detectingcircuit.
 35. The semiconductor memory device as claimed in claim 33 ,further comprising: a main virtual ground line selector circuit forselecting at least one of said main virtual ground lines, so that saidselected at least one main virtual ground line is connected to a groundline; and a reference virtual ground selector circuit for selecting atleast one of said reference virtual ground lines, so that said selectedat least one reference virtual ground line is also connected to saidground line.
 36. The semiconductor memory device as claimed in claim 33, wherein said memory cell region further includes subordinate memorydigit lines, and said reference cell region further includes subordinatereference digit lines, and further comprising a bank selecting circuitfor selecting at least one of said subordinate memory digit lines, sothat said selected at least one subordinate memory digit line isconnected to said main digit line, and further selecting at least one ofsaid subordinate reference digit lines, so that said selected at leastone subordinate reference digit line is connected to said referencedigit line.
 37. The semiconductor memory device as claimed in claim 33 ,further comprising a main pre-charge circuit, and wherein at leastsecond one of said main digit lines is selected and connected to saidmain pre-charge circuit, wherein said at least first one main digit lineconnected to said current detecting circuit, said at least second one ofsaid main digit line connected to said main pre-charge circuit, and saidat least first one main virtual ground line connected to said groundline form a second main current route, wherein at least second one ofsaid reference digit lines is selected and connected to said mainpre-charge circuit, wherein said at least first one reference digit lineconnected to said current detecting circuit, said at least second onereference digit line connected to said main pre-charge circuit, and saidat least first one reference virtual ground line connected to saidground line form a first reference current route, which is identicalwith said first main current route.
 38. The semiconductor memory deviceas claimed in claim 37 , further comprising a subordinate pre-chargecircuit, and wherein at least second one of said main virtual groundlines is selected and connected to said subordinate pre-charge circuit,wherein said at least first one main digit line connected to saidcurrent detecting circuit, said at least second one of said main digitline connected to said subordinate pre-charge circuit, said at leastfirst one main virtual ground line connected to said ground line, andsaid second one main virtual ground line form a third main currentroute, wherein at least second one of said reference virtual groundlines is selected and connected to said subordinate pre-charge circuit,and wherein said at least first one reference digit line connected tosaid current detecting circuit, said at least second one reference digitline connected to said subordinate pre-charge circuit, said at leastfirst one reference virtual ground line connected to said ground line,and said at least second one reference virtual ground line form a fourthreference current route, which is identical with said third main currentroute.
 39. The semiconductor memory device as claimed in claim 33 ,further comprising: subordinate memory digit lines in said memory cellregion; subordinate reference digit lines in said reference cell regionand at least a bank selecting circuit for selecting at least one of saidsubordinate memory digit lines and connecting said selected at least onesubordinate memory digit line to said main digit line, as well as forselecting at least one of said subordinate reference digit lines andconnecting said selected at least one subordinate reference digit lineto said reference digit line.
 40. A semiconductor memory devicecomprising; a memory cell region including a plurality of main banks,each having memory cells, main digit lines, main virtual ground lines,subordinate digit lines, and subordinate virtual ground lines; a maindigit line selector circuit being connected to said main digit lines forselecting at least one of said main digit lines; a main virtual groundselector circuit being connected to said main virtual ground lines forselecting at least one of said main virtual ground lines; a referencecell region including a plurality of reference banks, each havingreference memory cells, reference digit lines, reference virtual groundlines, subordinate reference digit lines and subordinate referencevirtual ground lines; a reference digit line selector circuit beingconnected to said reference digit lines for selecting at least one ofsaid reference digit lines; a reference virtual ground selector circuitbeing connected to said reference virtual ground lines for selecting atleast one of said reference virtual ground lines; a bank selectingcircuit connected to said subordinate digit lines and said referencesubordinate digit lines for selecting at least one of said subordinatedigit lines and connecting said at least one subordinate digit line tosaid main digit line, and further selecting at least one of saidsubordinate reference digit lines and connecting said at least onesubordinate reference digit line to said reference digit line; and aground selecting circuit connected to said subordinate main virtualground lines and said subordinate reference virtual ground lines forselecting at least one of said subordinate main virtual ground lines andconnecting said at least one subordinate main virtual ground line tosaid main virtual ground line, and further selecting at least one ofsaid subordinate reference virtual ground lines and connecting said atleast one subordinate reference virtual ground line to said referencevirtual ground line, wherein said reference cell region hassubstantially the same interconnection routine as said memory cellregion.
 41. The semiconductor memory device as claimed in claim 40 ,wherein in said reference cell region, adjacent reference cells to aselected reference cell to be referred are off-bit cells.
 42. Thesemiconductor memory device as claimed in claim 40 , wherein said memorycell region possesses a first current routine pattern through said maindigit line to said main memory cell designated in accordance with aaddress signal, and said reference cell region possesses a secondcurrent routine pattern through said reference digit line to saidreference memory cell in accordance with said address signal, andwherein said first current routine pattern is always identical with saidsecond current routine pattern upon designating any memory celladdresses.
 43. The semiconductor memory device as claimed in claim 40 ,wherein said reference cell region includes adjacent first and secondsubordinate regions, and said first subordinate region having evennumber banks having ON-bit cells and odd number banks having OFF-bitcells, and said second subordinate region having even number bankshaving OFF-bit cells and odd number banks having ON-bit cells.
 44. Asemiconductor memory device comprising: a memory cell region including aplurality of main banks, each having memory cells, main digit lines,main virtual ground lines, subordinate digit lines, and subordinatevirtual ground lines; a main digit line selector circuit being connectedto said main digit lines for selecting at least one of said main digitlines; a main virtual ground selector circuit being connected to saidmain virtual ground lines for selecting at least one of said mainvirtual ground lines; a reference cell region including a plurality ofreference banks, each having reference memory cells, reference digitlines, reference virtual ground lines, subordinate reference digit linesand subordinate reference virtual ground lines; a reference digit lineselector circuit being connected to said reference digit lines forselecting at least one of said reference digit lines; a referencevirtual ground selector circuit being connected to said referencevirtual ground lines for selecting at least one of said referencevirtual ground lines; a bank selecting circuit connected to saidsubordinate digit lines and said reference subordinate digit lines forselecting at least one of said subordinate digit lines and connectingsaid at least one subordinate digit line to said main digit line, andfurther selecting at least one of said subordinate reference digit linesand connecting said at least one subordinate reference digit line tosaid reference digit line; and a ground selecting circuit connected tosaid subordinate main virtual ground lines and said subordinatereference virtual ground lines for selecting at least one of saidsubordinate main virtual ground lines and connecting said at least onesubordinate main virtual ground line to said main virtual ground line,and further selecting at least one of said subordinate reference virtualground lines and connecting said at least one subordinate referencevirtual ground line to said reference virtual ground line, wherein insaid reference cell region, adjacent reference cells to a selectedreference cell to be referred are off-bit cells.
 45. The semiconductormemory device as claimed in claim 44 , wherein said reference cellregion has substantially the same interconnection routine as said memorycell region.
 46. The semiconductor memory device as claimed in claim 44, wherein said memory cell region possesses a first current routinepattern through said main digit line to said main memory cell designatedin accordance with a address signal, and said reference cell regionpossesses a second current routine pattern through said reference digitline to said reference memory cell in accordance with said addresssignal, and wherein said first current routine pattern is alwaysidentical with said second current routine pattern upon designating anymemory cell addresses.
 47. The semiconductor memory device as claimed inclaim 44 , wherein said reference cell region includes adjacent firstand second subordinate regions, and said first subordinate region havingeven number banks having ON-bit cells and odd number banks havingOFF-bit cells, and said second subordinate region having even numberbanks having OFF-bit cells and odd number banks having ON-bit cells. 48.A semiconductor memory device comprising: a memory cell region includinga plurality of main banks, each having memory cells, main digit lines,main virtual ground lines, subordinate digit lines, and subordinatevirtual ground lines; a main digit line selector circuit being connectedto said main digit lines for selecting at least one of said main digitlines; a main virtual ground selector circuit being connected to saidmain virtual ground lines for selecting at least one of said mainvirtual ground lines; a reference cell region including a plurality ofreference banks, each having reference memory cells, reference digitlines, reference virtual ground lines, subordinate reference digit linesand subordinate reference virtual ground lines; a reference digit lineselector circuit being connected to said reference digit lines forselecting at least one of said reference digit lines; a referencevirtual ground selector circuit being connected to said referencevirtual ground lines for selecting at least one of said referencevirtual ground lines; a bank selecting circuit connected to saidsubordinate digit lines and said reference subordinate digit lines forselecting at least one of said subordinate digit lines and connectingsaid at least one subordinate digit line to said main digit line, andfurther selecting at least one of said subordinate reference digit linesand connecting said at least one subordinate reference digit line tosaid reference digit line; and a ground selecting circuit connected tosaid subordinate main virtual ground lines and said subordinatereference virtual ground lines for selecting at least one of saidsubordinate main virtual ground lines and connecting said at least onesubordinate main virtual ground line to said main virtual ground line,and further selecting at least one of said subordinate reference virtualground lines and connecting said at least one subordinate referencevirtual ground line to said reference virtual ground line, wherein saidmemory cell region possesses a first current routine pattern throughsaid main digit line to said main memory cell designated in accordancewith a address signal, and said reference cell region possesses a secondcurrent routine pattern through said reference digit line to saidreference memory cell in accordance with said address signal, andwherein said first current routine pattern is always identical with saidsecond current routine pattern upon designating any memory celladdresses.
 49. The semiconductor memory device as claimed in claim 48 ,wherein said reference cell region has substantially the sameinterconnection routine as said memory cell region.
 50. Thesemiconductor memory device as claimed in claim 48 , wherein in saidreference cell region, adjacent reference cells to a selected referencecell to be referred are off-bit cells.
 51. The semiconductor memorydevice as claimed in claim 48 , wherein said reference cell regionincludes adjacent first and second subordinate regions, and said firstsubordinate region having even number banks having ON-bit cells and oddnumber banks having OFF-bit cells, and said second subordinate regionhaving even number banks having OFF-bit cells and odd number bankshaving ON-bit cells.
 52. A semiconductor memory device comprising: amemory cell region including a plurality of main banks, each havingmemory cells, main digit lines, main virtual ground lines, subordinatedigit lines, and subordinate virtual ground lines; a main digit lineselector circuit being connected to said main digit lines for selectingat least one of said main digit lines; a main virtual ground selectorcircuit being connected to said main virtual ground lines for selectingat least one of said main virtual ground lines; a reference cell regionincluding a plurality of reference banks, each having reference memorycells, reference digit lines, reference virtual ground lines,subordinate reference digit lines and subordinate reference virtualground lines; a reference digit line selector circuit being connected tosaid reference digit lines for selecting at least one of said referencedigit lines; a reference virtual ground selector circuit being connectedto said reference virtual ground lines for selecting at least one ofsaid reference virtual ground lines; a bank selecting circuit connectedto said subordinate digit lines and said reference subordinate digitlines for selecting at least one of said subordinate digit lines andconnecting said at least one subordinate digit line to said main digitline, and further selecting at least one of said subordinate referencedigit lines and connecting said at least one subordinate reference digitline to said reference digit line ; and a ground selecting circuitconnected to said subordinate main virtual ground lines and saidsubordinate reference virtual ground lines for selecting at least one ofsaid subordinate main virtual ground lines and connecting said at leastone subordinate main virtual ground line to said main virtual groundline, and further selecting at least one of said subordinate referencevirtual ground lines and connecting said at least one subordinatereference virtual ground line to said reference virtual ground line,wherein said reference cell region includes adjacent first and secondsubordinate regions, and said first subordinate region having evennumber banks having ON-bit cells and odd number banks having OFF-bitcells, and said second subordinate region having even number bankshaving OFF-bit cells and odd number banks having ON-bit cells.
 53. Thesemiconductor memory device as claimed in claim 52 , wherein saidreference cell region has substantially the same interconnection routineas said memory cell region.
 54. The semiconductor memory device asclaimed in claim 52 , wherein in said reference cell region, adjacentreference cells to a selected reference cell to be referred are off-bitcells.
 55. The semiconductor memory device as claimed in claim 52 ,wherein said memory cell region possesses a first current routinepattern through said main digit line to said main memory cell designatedin accordance with a address signal, and said reference cell regionpossesses a second current routine pattern through said reference digitline to said reference memory cell in accordance with said addresssignal, and wherein said first current routine pattern is alwaysidentical with said second current routine pattern upon designating anymemory cell addresses.